Early detection of programming failure for non-volatile memory

ABSTRACT

An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.

BACKGROUND

Semiconductor memory is widely used in various electronic devices suchas cellular telephones, digital cameras, personal digital assistants,medical electronics, mobile computing devices, servers, solid statedrives, non-mobile computing devices and other devices. Semiconductormemory may comprise non-volatile memory or volatile memory. Anon-volatile memory allows information to be stored and retained evenwhen the non-volatile memory is not connected to a source of power(e.g., a battery). Examples of non-volatile memory include flash memory(e.g., NAND-type and NOR-type flash memory).

Memory systems can be used to store data provided by a host device (orother client). However, various challenges are presented in operatingsuch memory systems. In particular, as memory cells decrease in size andmemory arrays increase in density, maintaining the integrity of databeing stored becomes more challenging.

BRIEF DESCRIPTION OF THE DRAWINGS

Like-numbered elements refer to common components in the differentfigures.

FIG. 1 is a block diagram depicting one embodiment of a memory system.

FIG. 2 is a block diagram of one embodiment of a memory die.

FIG. 3 is a perspective view of a portion of one embodiment of a threedimensional memory structure.

FIG. 4A is a block diagram of a memory structure having two planes.

FIG. 4B depicts a top view of a portion of a block of memory cells.

FIG. 4C depicts a cross sectional view of a portion of a block of memorycells.

FIG. 4D depicts a view of the select gate layers and word line layers.

FIG. 4E is a cross sectional view of a memory hole of memory cells.

FIG. 4F is a schematic of a plurality of NAND strings.

FIG. 5A depicts an embodiment of threshold voltage distributions for afour-state memory device in which each memory cell stores two bits ofdata.

FIG. 5B depicts an embodiment of threshold voltage distributions for aneight-state memory device in which each memory cell stores three bits ofdata.

FIG. 5C depicts an embodiment of threshold voltage distributions for asixteen-state memory device in which each memory cell stores four bitsof data.

FIG. 6 depicts threshold voltage distributions and describe a processfor programming non-volatile memory.

FIGS. 7A-7E depict various threshold voltage distributions and describea process for programming non-volatile memory.

FIG. 8 is a flowchart describing an embodiment of a process forprogramming non-volatile memory.

FIG. 9 depicts a word line voltage during programming and verifyoperations.

FIG. 10A is a flowchart describing an embodiment of a process forprogramming non-volatile memory.

FIG. 10B is a flowchart describing an embodiment of a process forprogramming non-volatile memory.

DETAILED DESCRIPTION

Technology is described for programming processes that include earlydetection of programming failure, word line failure and/or blockfailure. In particular, programming processes that include earlydetection of programming failure, word line failure and/or block failurebased on detecting a deviation in program completion loops fornon-volatile memory.

Some non-volatile memory devices are used to store two ranges of chargesand, therefore, the memory cells can be programmed/erased between twodata states: an erased state and a programmed state (corresponding todata “1” and data “0”). Such a device is referred to as a binary deviceor a single-level cell (SLC) and the data are binary data.

In contrast, a multi-state flash memory cell (storing multi-state data)is implemented by identifying multiple, distinct allowed thresholdvoltage ranges. Each distinct threshold voltage range corresponds to apredetermined value for the set of data bits. For example, some memorycells can store two or more bits. The specific relationship between thedata programmed into the memory cell and the threshold voltage ranges ofthe memory cell depends upon the data encoding scheme adopted for thememory cells.

In addition to the gains in capacity resulting from multi-state memoryarchitectures, significant advantages in memory technology have resultedfrom steadily scaling down the physical dimensions of memory cells.Smaller memory cells can be packed more densely on a given die area,allowing higher memory capacity for the same price as an older memorytechnology.

FIG. 1 is a block diagram of an embodiment of a memory system 100 thatimplements the described technology. In an embodiment, memory system 100is a solid state drive (“SSD”). Memory system 100 also can be a memorycard, USB drive or other type of storage system. The proposed technologyis not limited to any one type of memory system. Memory system 100 isconnected to host 102, which can be a computer, server, electronicdevice (e.g., smart phone, tablet or other mobile device), appliance, oranother apparatus that uses memory and has data processing capabilities.In some embodiments, host 102 is separate from, but connected to, memorysystem 100. In other embodiments, memory system 100 is embedded withinhost 102.

The components of memory system 100 depicted in FIG. 1 are electricalcircuits. Memory system 100 includes a controller 104 connected to oneor more memory die 106 and local high speed volatile memory 108 (e.g.,DRAM). The one or more memory die 106 each include a plurality ofnon-volatile memory cells. More information about the structure of eachmemory die 106 is provided below. Local high speed volatile memory 108is used by controller 104 to perform certain functions. For example,local high speed volatile memory 108 stores logical to physical addresstranslation tables (“L2P tables”)

Controller 104 includes a host interface 110 that is connected to and incommunication with host 102. In one embodiment, host interface 110provides a PCIe interface. Other interfaces can also be used, such asSCSI, SATA, etc. Host interface 110 is also connected to anetwork-on-chip (NOC) 112, which is a communication subsystem on anintegrated circuit. In other embodiments, NOC 112 can be replaced by abus.

A NOC can span synchronous and asynchronous clock domains or useun-clocked asynchronous logic. NOC technology applies networking theoryand methods to on-chip communications and brings notable improvementsover conventional bus and crossbar interconnections. NOC improves thescalability of systems on a chip (SoC) and the power efficiency ofcomplex SoCs compared to other designs. In embodiments, the wires andthe links of a NOC are shared by many signals. A high level ofparallelism is achieved because all links in the NOC can operatesimultaneously on different data packets. Therefore, as the complexityof integrated subsystems keep growing, a NOC provides enhancedperformance (such as throughput) and scalability in comparison withprevious communication architectures (e.g., dedicated point-to-pointsignal wires, shared buses, or segmented buses with bridges).

Connected to and in communication with NOC 112 is processor 114, ECCengine 116, memory interface 118, and DRAM controller 120. DRAMcontroller 120 is used to operate and communicate with local high speedvolatile memory 108 (e.g., DRAM). In other embodiments, local high speedvolatile memory 108 can be SRAM or another type of volatile memory.

ECC engine 116 performs error correction services. For example, ECCengine 116 performs data encoding and decoding, as per the implementedECC technique. In one embodiment, ECC engine 116 is an electricalcircuit programmed by software. For example, ECC engine 116 can be aprocessor that can be programmed. In other embodiments, ECC engine 116is a custom and dedicated hardware circuit without any software. Inanother embodiment, the function of ECC engine 116 is implemented byprocessor 114.

Processor 114 performs the various controller memory operations, such asprogramming, erasing, reading, as well as memory management processes.In an embodiment, processor 114 is programmed by firmware. In otherembodiments, processor 114 is a custom and dedicated hardware circuitwithout any software. In an embodiment, processor 114 also implements atranslation module, as a software/firmware process or as a dedicatedhardware circuit.

In many systems, non-volatile memory is addressed internally to thestorage system using physical addresses associated with the one or morememory die. However, the host system will use logical addresses toaddress the various memory locations. This enables the host to assigndata to consecutive logical addresses, while the storage system is freeto store the data as it wishes among the locations of the one or morememory die. To enable this system, the controller (e.g., the translationmodule) performs address translation between the logical addresses usedby the host and the physical addresses used by the memory dies.

One example implementation is to maintain tables (e.g., the L2P tablesmentioned above) that identify a translation between logical addressesand physical addresses. An entry in the L2P table may include anidentification of a logical address and corresponding physical address.Although logical address to physical address tables (or L2P tables)include the word “tables” they need not literally be tables. Rather, thelogical address to physical address tables (or L2P tables) can be anytype of data structure.

In some examples, the memory space of a storage system is so large thatlocal memory 108 cannot hold all of the L2P tables. In such a case, theentire set of L2P tables are stored in a memory die 106 and a subset ofthe L2P tables are cached (L2P cache) in the local high speed volatilememory 108.

In an embodiment, memory interface 118 communicates with one or morememory die 106. In an embodiment, memory interface 118 provides a ToggleMode interface. Other interfaces also can be used. In some exampleimplementations, memory interface 118 (or another portion of controller104) implements a scheduler and buffer for transmitting data to andreceiving data from one or more memory die.

FIG. 2 is a functional block diagram of one embodiment of a memory die200. Each of the one or more memory die 106 of FIG. 1 can be implementedas memory die 200 of FIG. 2 . The components depicted in FIG. 2 areelectrical circuits. In an embodiment, each memory die 200 includes amemory structure 202, control circuitry 204, and read/write circuits206. Memory structure 202 is addressable by word lines via a row decoder208 and by bit lines via a column decoder 210.

In an embodiment, read/write circuits 206 include multiple sense blocks212 including SB1, SB2, . . . SBp (sensing circuitry) and allow a page(or multiple pages) of data in multiple memory cells to be read orprogrammed (written) in parallel. In an embodiment, each sense block 212include a sense amplifier and a set of latches connected to the bitline. The latches store data to be written and/or data that has beenread. In an embodiment, each sense amplifier 212 includes bit linedrivers. In an embodiment, commands and data are transferred betweencontroller 104 and memory die 200 via lines 214. In an embodiment,memory die 200 includes a set of input and/or output (I/O) pins thatconnect to lines 214.

In an embodiment, control circuitry 204 cooperates with read/writecircuits 206 to perform memory operations (e.g., write, read, erase, andothers) on memory structure 202. In an embodiment, control circuitry 204includes a state machine 216, an on-chip address decoder 218, and apower control circuit 220. In an embodiment, state machine 216 providesdie-level control of memory operations. In an embodiment, state machine216 is programmable by software. In other embodiments, state machine 216does not use software and is completely implemented in hardware (e.g.,electrical circuits). In some embodiments, state machine 216 can bereplaced by a microcontroller or microprocessor. In an embodiment,control circuitry 204 includes buffers such as registers, ROM fuses andother storage devices for storing default values such as base voltagesand other parameters.

On-chip address decoder 218 provides an address interface betweenaddresses used by controller 104 to the hardware address used by rowdecoder 208 and column decoder 210. Power control module 220 controlsthe power and voltages supplied to the word lines and bit lines duringmemory operations. Power control module 220 may include charge pumps forcreating voltages.

For purposes of this document, control circuitry 204, read/writecircuits 206, row decoder 208 and column decoder 210 comprise a “ControlCircuit” for memory structure 202. In other embodiments, other circuitsthat support and operate on memory structure 202 can be referred to as aControl Circuit. For example, in some embodiments, controller 104 canoperate as the Control Circuit or can be part of the Control Circuit.The Control Circuit also can be implemented as a microprocessor or othertype of processor that is hardwired or programmed to perform thefunctions described herein.

For purposes of this document, control circuitry 204, read/writecircuits 206, row decoder 208 and column decoder 210 comprise peripheralcircuits for memory structure 202, as they are not part of memorystructure 202 but are on the same die as memory structure 202 and areused to operate memory structure 202.

In an embodiment, memory structure 202 is a three dimensional memoryarray of non-volatile memory cells. In an embodiment, memory structure202 is a monolithic three dimensional memory array in which multiplememory levels are formed above a single substrate, such as a wafer. Thememory structure may be any type of non-volatile memory that is formedin one or more physical levels of arrays of memory cells having anactive area disposed above a silicon (or other type of) substrate. Inone example, the non-volatile memory cells of memory structure 202include vertical NAND strings with charge-trapping material such asdescribed. A NAND string includes memory cells connected by a channel.

In another embodiment, memory structure 202 includes a two dimensionalmemory array of non-volatile memory cells. In an example, thenon-volatile memory cells are NAND flash memory cells utilizing floatinggates. Other types of memory cells (e.g., NOR-type flash memory) alsocan be used.

The exact type of memory array architecture or memory cell included inmemory structure 202 is not limited to the examples above. Manydifferent types of memory array architectures or memory celltechnologies can be used to form memory structure 202. No particularnon-volatile memory technology is required for purposes of the newtechnology described herein.

Other examples of suitable technologies for memory cells of the memorystructure 202 include ReRAM memories, magnetoresistive memory (MRAM),phase change memory (PCM), and the like. Examples of suitabletechnologies for architectures of memory structure 202 include twodimensional arrays, three dimensional arrays, cross-point arrays,stacked two dimensional arrays, vertical bit line arrays, and the like.

One example of a cross point memory includes reversibleresistance-switching elements arranged in cross point arrays accessed byX lines and Y lines (e.g., word lines and bit lines). In anotherembodiment, the memory cells may include conductive bridge memoryelements. A conductive bridge memory element also may be referred to asa programmable metallization cell.

A conductive bridge memory element may be used as a state change elementbased on the physical relocation of ions within a solid electrolyte. Insome cases, a conductive bridge memory element may include two solidmetal electrodes, one relatively inert (e.g., tungsten) and the otherelectrochemically active (e.g., silver or copper), with a thin film ofsolid electrolyte between the two electrodes.

MRAM stores data using magnetic storage elements. The magnetic storageelements are formed from two ferromagnetic plates, each of which canhold a magnetization, separated by a thin insulating layer. One of thetwo plates is a permanent magnet set to a particular polarity; the otherplate's magnetization can be changed to match that of an external fieldto store memory. A memory device is built from a grid of such memorycells. In one embodiment for programming, each memory cell lies betweena pair of write lines arranged at right angles to each other, parallelto the cell, one above and one below the cell. When current is passedthrough them, an induced magnetic field is created.

Phase change memory (PCM) exploits the unique behavior of chalcogenideglass. One embodiment uses a GeTe—Sb₂Te₃ super lattice to achievenon-thermal phase changes by simply changing the coordination state ofGermanium atoms with a laser pulse (or light pulse from another source).Therefore, the doses of programming are laser pulses. The memory cellscan be inhibited from programming by blocking the memory cells fromreceiving the light.

A person of ordinary skill in the art will recognize that the technologydescribed herein is not limited to a single specific memory structure,but covers many relevant memory structures within the scope of thetechnology as described herein and as understood by one of ordinaryskill in the art.

FIG. 3 is a perspective view of a portion of an embodiment of a threedimensional memory array that includes memory structure 202. In anembodiment, memory structure 202 includes multiple non-volatile memorycells. For example, FIG. 3 shows a portion of one block of memory cells.The structure depicted includes a set of bit lines BL positioned above astack of alternating dielectric layers and conductive layers. Forexample purposes, one of the dielectric layers is marked as D and one ofthe conductive layers (also called word line layers) is marked as W.

The number of alternating dielectric layers and conductive layers canvary based on specific implementation requirements. One set ofembodiments includes between 108-300 alternating dielectric layers andconductive layers. One example embodiment includes 96 data word linelayers, 8 select layers, 6 dummy word line layers and 110 dielectriclayers. More or less than 108-300 layers also can be used. In anembodiment, the alternating dielectric layers and conductive layers aredivided into four regions by local interconnects LI. FIG. 3 shows tworegions and two local interconnects LI.

A source line layer SL is below the alternating dielectric layers andword line layers. Memory holes are formed in the stack of alternatingdielectric layers and conductive layers. For example, one of the memoryholes is marked as MH. Note that in FIG. 3 the dielectric layers aredepicted as see-through so that the reader can see the memory holespositioned in the stack of alternating dielectric layers and conductivelayers.

In an embodiment, NAND strings are formed by filling the memory holewith materials including a charge-trapping material to create a verticalcolumn of memory cells (also referred to as a memory column). In anembodiment, each memory cell can store one or more bits of data. In anembodiment, each memory hole MH is associated with and coupled to acorresponding one of bit lines BL. In an embodiment, each bit line BL iscoupled to one or more memory holes MH. More details of a threedimensional memory array that comprises memory structure 202 aredescribed below.

FIG. 4A is a block diagram explaining one example organization of memorystructure 202, which is divided into two planes 400 a and 400 b. Bothplanes are on the same memory die 200 (FIG. 2 ). Each plane is thendivided into M blocks. In one example, each plane has about 2000 blocks.However, different numbers of blocks and planes also can be used. Aportion 402 of block 2 of memory plane 400 a is shown in dashed line inFIG. 4A.

In an embodiment, a block of memory cells is a unit of erase. That is,all memory cells of a block are erased together. In other embodiments,memory cells can be grouped into blocks for other reasons, such as toorganize memory structure 202 to enable the signaling and selectioncircuits. In some embodiments, a block represents a group of connectedmemory cells as the memory cells of a block share a common set of wordlines. Although FIG. 4A shows two planes on the same die, in otherembodiments more than two planes can be implemented. For example, memorystructure 202 can include 2-8 (or more) planes.

FIGS. 4B-4F depict an example three dimensional (“3D”) NAND structurethat corresponds to the structure of FIG. 3 . FIG. 4B is a block diagramdepicting a top view of portion 402 (FIG. 4A) of memory structure 202.As can be seen from FIG. 4B, portion 402 extends in direction 404 anddirection 406. In an embodiment, the memory array has many layers,however, FIG. 4B only shows the top layer.

FIG. 4B depicts a plurality of circles that represent the memory holes,which are also referred to as memory columns. For example, FIG. 4Bdepicts memory holes 408, 410, 412 and 414. Each of the memory holesinclude multiple select transistors (also referred to as a select gateor selection gate) and multiple memory cells. In an embodiment, eachmemory hole implements a NAND string. Because portion 402 extends indirections 404 and 406, the block includes more memory holes thandepicted in FIG. 4B.

FIG. 4B also depicts a set of bit lines 424, including bit lines 426,428, 430, 432, . . . 434. In an embodiment, each memory hole isassociated with and coupled to a corresponding one of the bit lines. Inan embodiment, each bit line is coupled to one or more memory holes.FIG. 4B shows twenty four bit lines because only a portion of the blockis depicted. It is contemplated that more than twenty four bit lines areconnected to memory holes of the block. Each of the circles representinga memory hole has an “x” to indicate its connection to one bit line. Forexample, bit line 432 is connected to memory holes 408, 410, 412 and414.

Portion 402 depicted in FIG. 4B includes a set of local interconnects436, 438, 440, 442 and 444 that connect the various layers to a sourceline below the memory holes. Local interconnects 436, 438, 440, 442 and444 also serve to divide each layer of the block into four regions. Forexample, the top layer depicted in FIG. 4B is divided into four regionsdesignated as String0, String1, Sting2 and String3. In the layers of theblock that implement memory cells, String0, String1, Sting2 and String3also may be referred to as word line fingers that are separated by thelocal interconnects.

In an embodiment, the word line fingers on a common level of a blockconnect together to form a single word line. In another embodiment, theword line fingers on the same level are not connected together. In anexample implementation, a bit line connects to a single memory hole ineach of String0, String1, Sting2 and String3. In that implementation,each block has sixteen rows of active columns and each bit line connectsto four rows in each block.

In an embodiment, all four rows connected to a common bit line areconnected to the same word line (via different word line fingers on thesame level that are connected together). Therefore, the system uses thesource side selection lines and the drain side selection lines to chooseone (or another subset) of the four to be subjected to a memoryoperation (program, verify, read, and/or erase).

Although FIG. 4B shows four regions String0, String1, Sting2 andString3, each having four rows of memory holes, and sixteen rows ofmemory holes in a block, those exact numbers are an exampleimplementation. Other embodiments may include more or less regions perblock, more or less rows of memory holes per region and more or lessrows of memory holes per block. FIG. 4B also shows the memory holesbeing staggered. In other embodiments, different patterns of staggeringcan be used. In some embodiments, the memory holes are not staggered.

FIG. 4C depicts a portion of one embodiment of a three dimensionalmemory structure 202 showing a cross-sectional view along line AA ofFIG. 4B. This cross sectional view cuts through memory holes 410 and 454of String1 (see FIG. 4B). The structure of FIG. 4C includes four drainside select layers SGD0, SGD1, SGD2 and SGD3, four source side selectlayers SGS0, SGS1, SGS2 and SGS3, six dummy word line layers DD0, DD1,DS0, DS1, WLDL, WLDU, and one hundred and twelve data word line layersWLL0-WLL111 for connecting to memory cells. Other embodiments canimplement more or less than four drain side select layers, more or lessthan four source side select layers, more or less than six dummy wordline layers, and more or less than one hundred and twelve word lines.

Memory holes 410 and 454 are depicted protruding through the drain sideselect layers, source side select layers, dummy word line layers andword line layers. In one embodiment, each memory hole includes avertical NAND string. Below the memory holes and the layers listed belowis substrate 456, an insulating film 458 on the substrate, and sourceline SL. The NAND string of memory hole 410 has a source end at a bottomof the stack and a drain end at a top of the stack. As in agreement withFIG. 4B, FIG. 4C shows memory hole 410 connected to bit line 432 viaconnector 460. Local interconnects 438 and 440 also are depicted.

For ease of reference, drain side select layers SGD0, SGD1, SGD2 andSGD3, source side select layers SGS0, SGS1, SGS2 and SGS3, dummy wordline layers DD0, DD1, DS0, DS1, WLDL and WLDU, and word line layersWLL0-WLL111 collectively are referred to as the conductive layers. In anembodiment, the conductive layers are made from a combination of TiN andtungsten. In other embodiments, other materials can be used to form theconductive layers, such as doped polysilicon, metal such as tungsten ormetal silicide. In some embodiments, different conductive layers can beformed from different materials.

Between conductive layers are dielectric layers DL0-DL127. For example,dielectric layer DL120 is above word line layer WLL110 and below wordline layer WLL111. In an embodiment, the dielectric layers are made fromSiO₂. In other embodiments, other dielectric materials can be used toform the dielectric layers.

The non-volatile memory cells are formed along memory holes which extendthrough alternating conductive and dielectric layers in the stack. In anembodiment, the memory cells are arranged in NAND strings. The word linelayers WLL0-WLL111 connect to memory cells (also called data memorycells). Dummy word line layers DD0, DD1, DS0, DS1, WLDL and WLDU connectto dummy memory cells. A dummy memory cell does not store and is noteligible to store host data (data provided from the host, such as datafrom a user of the host), while a data memory cell is eligible to storehost data.

In some embodiments, data memory cells and dummy memory cells may have asame structure. A dummy word line is connected to dummy memory cells.Drain side select layers SGD0, SGD1, SGD2 and SGD3 are used toelectrically connect and disconnect NAND strings from bit lines. Sourceside select layers SGS0, SGS1, SGS2 and SGS3 are used to electricallyconnect and disconnect NAND strings from the source line SL.

FIG. 4C also shows a “Joint Area.” In an embodiment it is expensiveand/or challenging to etch one hundred and twelve word line layersintermixed with dielectric layers. To ease this burden, one embodimentincludes laying down a first stack of fifty-six word line layersalternating with dielectric layers, laying down the Joint Area, andlaying down a second stack of fifty-six word line layers alternatingwith dielectric layers. The Joint Area is positioned between the firststack and the second stack. The Joint Area is used to connect the firststack to the second stack.

In FIG. 4C, the first stack is labeled as the “Lower Set of Word Lines”and the second stack is labeled as the “Upper Set of Word Lines.” In anembodiment, the Joint Area is made from the same materials as the wordline layers. In one example set of implementations, the plurality ofword lines (control lines) comprises a first stack of alternating wordline layers and dielectric layers, a second stack of alternating wordline layers and dielectric layers, and a joint area between the firststack and the second stack, as depicted in FIG. 4C.

FIG. 4D depicts a logical representation of the conductive layers (SGD0,SGD1, SGD2, SGD3, SGS0, SGS1, SGS2, SGS3, DD0, DD1, DS0, DS1, andWLL0-WLL111) for the block that is partially depicted in FIG. 4C. Asmentioned above with respect to FIG. 4B, in an embodiment localinterconnects 436, 438, 440, 442 and 444 break up the conductive layersinto four regions/fingers.

For example, word line layer WLL110 is divided into regions String0_(w110), String1 _(w110), String2 _(w110) and String3 _(w110). In anembodiment, the four word line fingers on a same level are connectedtogether. In another embodiment, each word line finger operates as aseparate word line.

Likewise, drain side select gate layer SGD0 (the top layer) is dividedinto regions Strin0 _(sGD0), String1 _(SGD0), String2 _(SGD0) andString3 _(SGD0), also known as fingers or select line fingers. In anembodiment, the four select line fingers on a same level are connectedtogether. In another embodiment, each select line finger operates as aseparate word line.

FIG. 4E depicts a cross sectional view of String1 of FIG. 4C thatincludes a portion of memory hole 410. In an embodiment, the memoryholes (e.g., memory hole 410) are shaped as cylinders. In otherembodiment, however, memory holes may have other shapes. In anembodiment, memory hole 410 includes an inner core layer 480, a channel482 surrounding inner core layer 480, a tunneling dielectric 484surrounding channel 482, and a charge trapping layer 486 surroundingtunneling dielectric 484. In an embodiment, inner core layer 480 adielectric material (e.g., SiO₂), channel 482 is polysilicon, tunnelingdielectric 484 has an ONO structure, and charge trapping layer 486 issilicon nitride. Other memory materials and structures can also be used.The technology described herein is not limited to any particularmaterial or structure.

FIG. 4E depicts dielectric layers DLL121, DLL120, DLL119, DLL118 andDLL117, as well as word line layers WLL107, WLL108, WLL109, WLL110, andWLL111. In an embodiment, each of the word line layers includes a wordline region 488 surrounded by an aluminum oxide layer 490, which issurrounded by a blocking oxide (SiO₂) layer 492. The physicalinteraction of the word line layers with the memory hole forms thememory cells. Thus, a memory cell, in an embodiment, includes channel482, tunneling dielectric 484, charge trapping layer 486, blocking oxidelayer 492, aluminum oxide layer 490 and word line region 488.

For example, word line layer WLL111 and a portion of memory hole 410comprise a memory cell MC1. Word line layer WLL110 and a portion ofmemory hole 410 comprise a memory cell MC2. Word line layer WLL109 and aportion of memory hole 410 comprise a memory cell MC3. Word line layerWLL108 and a portion of memory hole 410 comprise a memory cell MC4. Wordline layer WLL107 and a portion of memory hole 410 comprise a memorycell MC5. In other architectures, a memory cell may have a differentstructure; however, the memory cell would still be the storage unit.

In an embodiment, when a memory cell is programmed, electrons are storedin a portion of the charge trapping layer 486 which is associated withthe memory cell. These electrons are drawn into the charge trappinglayer 486 from the channel 482, through the tunneling dielectric 484, inresponse to an appropriate voltage on word line region 488. Thethreshold voltage of a memory cell is increased in proportion to theamount of stored charge.

In an embodiment, programming a memory cell is achieved throughFowler-Nordheim tunneling of the electrons into charge trapping layer486. During an erase operation, the electrons return to channel 482 orholes are injected into charge trapping layer 486 to recombine withelectrons. In an embodiment, erasing is achieved using hole injectioninto charge trapping layer 486 via a physical mechanism such as gateinduced drain leakage (GIDL).

FIG. 4F is a schematic diagram of corresponding to portion 402 in Block2 of FIGS. 4A-E, including bit lines 426, 428, 430, 432, . . . 434, andword lines WLL0-WLL111. Within the block, each bit line is connected tofour NAND strings. Drain side selection lines SGD0, SGD1, SGD2 and SGD3are used to determine which of the four NAND strings connect to theassociated bit line(s). Source side selection lines SGS0, SGS1, SGS2 andSGS3 are used to determine which of the four NAND strings connect to thecommon source line.

During any given memory operation, a subset of the memory cells will beidentified to be subjected to one or more parts of the memory operation.These memory cells identified to be subjected to the memory operationare referred to as selected memory cells. Memory cells that have notbeen identified to be subjected to the memory operation are referred toas unselected memory cells. Depending on the memory architecture, thememory type, and the memory operation, unselected memory cells may beactively or passively excluded from being subjected to the memoryoperation.

During a memory operation some word lines are referred to as selectedword lines because they are connected to selected memory cells.Unselected word lines are not connected to selected memory cells.Similarly, selected bit lines are connected to selected memory cells andunselected bit lines are not connected to selected memory cells.

Although the example memory system of FIG. 3 and FIGS. 4A-4F is a threedimensional memory structure that includes vertical NAND strings withcharge-trapping material, other (2D and 3D) memory structures also canbe used with the technology described herein.

The memory systems discussed above can be erased, programmed and read.At the end of a successful programming process (with verification), thethreshold voltages of the memory cells should be within one or moredistributions of threshold voltages for programmed memory cells orwithin a distribution of threshold voltages for erased memory cells, asappropriate.

Each memory cell may be associated with a memory state according towrite data in a program command. Based on its memory state, a memorycell will either remain in the erased state or be programmed to a memorystate (a programmed state) different from the erased state. For example,in a two-bit per cell memory device, there are four memory statesincluding the erased state (S0) and three programmed states referred toas the S1, S2 and S3 programmed states.

In a three-bit per cell memory device, there are eight memory statesincluding the erased state S0 and seven programmed states referred to asthe S1, S2, S3, S4, S5, S6 and S7 programmed states. In a four-bit percell memory device, there are sixteen memory states including the erasedstate S0 and fifteen programmed states referred to as the S1, S2, S3,S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 and S15 programmedstates.

FIG. 5A depicts an embodiment of threshold voltage distributions for afour-state memory device in which each memory cell stores two bits ofdata. A first Vth distribution 500 is provided for erased state (S0)storage elements. Three Vth distributions 502, 504 and 506 representprogrammed states S1, S2 and S3, respectively. A 2-bit code having lowerand upper bits can be used to represent each of the four memory states.In an embodiment, the “S0,” “S1,” “S2,” and “S3” memory states arerespectively represented by “11,” “01,” “00,” and “10.”

FIG. 5B depicts an embodiment of threshold voltage distributions for aneight-state memory device in which each memory cell stores three bits ofdata. A first Vth distribution 510 is provided for erased state (S0)storage elements. Seven Vth distributions 512, 514, 516, 518, 520, 522and 524 represent programmed states S1, S2, S3, S4, S5, S6 and S7,respectively. A 3-bit code having lower, middle and upper bits can beused to represent each of the eight memory states. In an embodiment, the“S0,” S1, S21, S3, S4, S5, S6 and S7 memory states are respectivelyrepresented by “111,” “011,” “001,” “101,” “100,” “000,” “010” and“110.”

FIG. 5B also shows seven verify reference voltages, Vv1, Vv2, Vv3, Vv4,Vv5, Vv6, and Vv7. When programming memory cells to programmed statesS1, S2, S3, S4, S5, S6 and S7, the system will test whether those memorycells have a threshold voltage greater than or equal to Vv1, Vv2, Vv3,Vv4, Vv5, Vv6 and Vv7, respectively.

FIG. 5C depicts an embodiment of threshold voltage distributions for asixteen-state memory device in which each memory cell stores four bitsof data. A first Vth distribution 530 is provided for erased state (S0)storage elements. Fifteen Vth distributions 532, 534, 536, 538, 540,542, 544, 546, 548, 550, 552, 554, 556, 558 and 560 represent programmedstates S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 andS15, respectively.

Referring again to FIG. 5B, seven verify reference voltages, Vv1, Vv2,Vv3, Vv4, Vv5, Vv6, and Vv7 are depicted. When programming memory cellsto programmed states S1, S2, S3, S4, S5, S6 and S7, the system will testwhether those memory cells have a threshold voltage greater than orequal to Vv1, Vv2, Vv3, Vv4, Vv5, Vv6 and Vv7, respectively.

In an embodiment, known as full sequence programming, memory cells canbe programmed from the erased state S0 directly to any of the programmedstates S1-S7. For example, referring to FIG. 6 , a population of memorycells to be programmed may first be erased so that all memory cells inthe population are in erased state S0. Then, a programming process isused to program memory cells directly into programmed states S1, S2, S3,S4, S5, S6, and/or S7. While some memory cells are being programmed fromerased state S0 to programmed state S1, other memory cells are beingprogrammed from erased state S0 to programmed state S2 and/or fromerased state S0 to programmed state S3, and so on.

The technology described herein also can be used with other types ofprogramming in addition to full sequence programming (including, but notlimited to, multiple stage/phase programming). In some embodiments,programmed states S1-S7 can overlap, with controller 104 (FIG. 1 )relying on error correction to identify the correct data being stored.

FIGS. 7A-7E illustrate a multi-phase programming approach. In thisembodiment, the programming process includes three phases. Prior toprogramming, the memory cells are erased so that all memory cellsconnected to a common word line are in an erased threshold voltagedistribution E, as depicted in FIG. 7A.

During the first programming phase, those memory cells whose targets(due to the data to be stored in those memory cells) are programmedstates S4, S5, S6 or S7 are programmed to an intermediate thresholdvoltage distribution IM. Those memory cells are targeted for programmedstates S0, S1, S2 or S3 remain in the erased threshold voltagedistribution E. The first phase is graphically depicted in FIG. 7B.Memory cells being programmed to intermediate threshold voltagedistribution IM are programmed to a target threshold voltage of VvIM.

During the second programming phase, those memory cells that are in theerased threshold voltage distribution E are programmed to their targetprogrammed states. For example, those memory cells to be programmed toprogrammed state S3 are programmed from erased threshold voltagedistribution E to programmed state S3, those memory cells to beprogrammed to programmed state S2 are programmed from erased thresholdvoltage distribution E to programmed state S2, those memory cells to beprogrammed to programmed state S1 are programmed from erase thresholdvoltage distribution E to programmed state S1, and those memory cells tobe in data state S0 are not programmed during the second phase of theprogramming process. Thus, erased threshold voltage distribution Ebecomes data state S0.

Also, during the second programming phase, those memory cells that arein the intermediate state threshold voltage distribution IM areprogrammed to their target programmed states. For example, those memorycells to be programmed to programmed state S7 are programmed fromintermediate threshold voltage distribution IM to programmed state S7,those memory cells to be programmed to programmed state S6 areprogrammed from intermediate threshold voltage distribution IM toprogrammed state S6, those memory cells to be programmed to programmedstate S5 are programmed from intermediate threshold voltage distributionIM to programmed state S5, and those memory cells to be in programmedstate S4 are programmed from intermediate threshold voltage distributionIM to programmed state S4. This second programming phase is illustratedin FIG. 7C.

As can be seen in FIG. 7C, at the end of the second programming phasedata states S1-S7 overlap with neighboring programmed states. Forexample, programmed state S1 overlaps with programmed state S2,programmed state S2 overlaps with programmed states S1 and S3,programmed state S3 overlaps with programmed states S2 and S4,programmed state S4 overlaps with programmed states S3 and S5,programmed state S5 overlaps with programmed states S4 and S6, and datastate S6 overlaps with programmed states S5 and S7. In some embodiments,all or some of the programmed states do not overlap.

In the third programming phase, each of programmed states S1-S7 aretightened so that they no longer overlap with neighboring states. Thisis depicted graphically by FIG. 7D. The final result of the three phraseprogramming process is depicted in FIG. 7E, which shows data statesS0-S7. In some embodiments, data state S0 is wider than programmedstates S1-S7. In an embodiment, the data states of FIGS. 7A-7E may beencoded according to the table of FIG. 6 .

In some embodiments, those memory cells to be programmed to programmedstate S4 are not programmed during the second phase and, therefore,remain in intermediate threshold voltage distribution IM. During thethird programming phase, the memory cells are programmed fromintermediate threshold voltage distribution IM to programmed state S4.In other embodiments, memory cells destined for other states can alsoremain in intermediate threshold voltage distribution IM or erasethreshold voltage distribution E during the second phase.

A programming operation for a set of memory cells typically involvesapplying a series of program voltage pulses to the memory cells afterthe memory cells are provided in an erased state. For example, theprogram voltage pulses may be applied to a word line which is connectedto control gates of the memory cells.

In one approach, incremental step pulse programming (ISPP) is performed,where the program voltage pulse amplitude is sequentially increased by astep size. Verify operations may be performed after each program voltagepulse to determine whether the memory cells have completed programming.When programming is completed for a memory cell, the memory cell can belocked out from further programming while programming continues forother memory cells.

FIG. 8 is a flowchart describing an embodiment of a process 800 forprogramming memory cells. In an example embodiment, process 800 isperformed on memory die 106 (FIG. 1 ) using the Control Circuitdiscussed above. For example, process 800 can be performed at thedirection of state machine 216 (FIG. 2 ). Process 800 also can be usedto implement the full sequence programming discussed above.Additionally, process 800 can be used to implement each phase of amulti-phase programming process.

At step 802, a word line is selected for programming. In an embodiment,the selected word line is coupled to one or more memory cells. In anembodiment, each memory cell coupled to the selected word line is in anerased state prior to programming. In an embodiment, during programmingeach memory cell coupled to the selected word line will be left in theerased state or programmed to one of multiple programmed states, such asthe programmed states depicted in FIGS. 5A-5C.

In step 804, a programming voltage (V_(P)) is initialized to a startingprogram voltage V_(Pinit) (e.g., between about 12V to about 16V, or someother value) and a program counter PC maintained by state machine 216 isinitialized at 1.

In step 806, a program pulse having a magnitude V_(P) is applied to theselected word line (the word line selected for programming). In anembodiment, the group of memory cells being concurrently programmed areall connected to the selected word line. If a memory cell is to beprogrammed, then the corresponding bit line coupled to the memory cellis grounded.

If a memory cell should remain at its current threshold voltage, thenthe corresponding bit line coupled to the memory cell is connected toVdd to inhibit programming. In an embodiment, the unselected word linesreceive one or more boosting voltages (e.g., between about 7V to about11V, or some other value) to perform boosting schemes known in the art.

In step 806, the program pulse is applied to all memory cells connectedto the selected word line so that all of the connected memory cells areprogrammed concurrently. That is, they are programmed at the same timeor during overlapping times (both of which are considered concurrent).In this manner all memory cells connected to the selected word line willconcurrently have their threshold voltage change, unless they have beenlocked out from programming.

In step 808, the memory cells are verified using the appropriate set ofverify reference voltages to perform one or more verify operations. Inan embodiment, the verification process is performed by testing whetherthe threshold voltages of the memory cells selected for programming havereached the appropriate verify reference voltage.

In step 810, the memory system counts the number of memory cells thathave not yet reached their respective target threshold voltagedistribution. That is, the system counts the number of memory cells thathave so far failed the verify process. This counting can be done by theControl Circuit described above, or other logic.

In an embodiment, each of sense blocks 212 (FIG. 2 ) stores the status(pass/fail) of their respective memory cells. In an embodiment, onetotal count reflects the total number of memory cells currently beingprogrammed that have failed the last verify step. In another embodiment,separate counts are kept for each data state.

In step 812, a determination is made whether the count from step 810 isless than or equal to a predetermined limit. In an embodiment, thepredetermined limit is the number of bits that can be corrected by errorcorrection codes (ECC) during a read process for the page of memorycells. If the number of failed cells is less than or equal to thepredetermined limit, than the programming process can stop and a statusof “PASS” is reported in step 814. In this situation, enough memorycells programmed correctly such that the few remaining memory cells thathave not been completely programmed can be corrected using ECC duringthe read process.

In some embodiments, the predetermined limit used in step 812 is belowthe number of bits that can be corrected by error correction codes (ECC)during a read process to allow for future/additional errors. Whenprogramming less than all of the memory cells for a page, or comparing acount for only one data state (or less than all states), then thepredetermined limit can be a portion (pro-rata or not pro-rata) of thenumber of bits that can be corrected by ECC during a read process forthe page of memory cells. In some embodiments, the limit is notpredetermined. Instead, the limit changes based on the number of errorsalready counted for the page, the number of program-erase cyclesperformed or other criteria.

If the number of failed memory cells is not less than the predeterminedlimit, then the programming process continues at step 816 and theprogram counter PC is checked against a program limit value (PLV). Anexample program limit value is PLV=28 although other values can be used.If the program counter PC is greater than or equal to program limitvalue PLV, then the program process is considered to have failed and astatus of FAIL is reported in step 818.

If the program counter PC is not greater than or equal to program limitvalue PLV, then the process continues at step 820 in which the ProgramCounter PC is incremented by 1 and program voltage V_(P) is stepped upto the next magnitude. For example, the next program pulse will have amagnitude greater than the previous pulse by a program step size ΔV_(P)(e.g., a step size of between about 0.1V to about 1.0V, or some othervalue).

Process 800 loops back to step 806 and another program pulse is appliedto the selected word line so that another iteration (steps 806-820) ofprogramming process 800 is performed. Each pass through steps 806-820 isreferred to herein as a “program loop.” The program limit value PLVdescribed above therefore specifies a maximum number of program loopsthat may be used to program the memory cells coupled to the selectedword line. The comparison performed at step 816 is referred to herein asa “maximum program count test.”

In general, during verify operations, the selected word line isconnected to a voltage (one example of a reference signal), a level ofwhich is specified for each verify operation (e.g. verify target levelsVv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 of FIG. 5B) to determine whether athreshold voltage of the selected memory cell has reached such level.

In an embodiment, after an appropriate read or verify voltage is appliedto a selected word line, a conduction current of the memory cell ismeasured to determine whether the memory cell turned ON (conductscurrent) in response to the voltage applied to the word line. If theconduction current is measured to be greater than a certain value, thenit is assumed that the memory cell turned ON and the voltage applied tothe word line is greater than the threshold voltage of the memory cell.

If the conduction current is measured to be not greater than the certainvalue, then the memory cell did not turn ON, and the voltage applied tothe word line is not greater than the threshold voltage of the memorycell. During a read or verify process, the unselected memory cells areprovided with one or more read pass voltages (also referred to as bypassvoltages) at their control gates so that these memory cells will operateas pass gates (e.g., conducting current regardless of whether they areprogrammed or erased).

There are many ways to measure the conduction current of a memory cellduring a read or verify operation. In one example, the conductioncurrent of a memory cell is measured by the rate at which the memorycell discharges or charges a dedicated capacitor in a sense amplifier.In another example, the conduction current of the selected memory cellallows (or fails to allow) the NAND string that includes the memory cellto discharge a corresponding bit line. The voltage on the bit line ismeasured after a period of time to see whether or not the bit line hasbeen discharged. Note that the technology described herein can be usedwith different methods known in the art for verifying/reading. Otherread and verify techniques known in the art also can be used.

As described above, at step 806 a program pulse is applied to theselected word line, and at step 808 memory cells coupled to the selectedword line are verified using an appropriate set of verify referencevoltages to perform one or more verify operations. Steps 806 and 808 arepart of an iterative loop in which program pulses are applied as aseries of program pulses that step up in magnitude, with interveningverify reference pulses between consecutive program pulses. Such aniterative loop is referred to herein as a “program-verify iteration.”

FIG. 9 illustrates an example of such program-verify pulses applied to aselected word line. In particular, FIG. 9 depicts program pulses 900,902 and 904 applied to the selected word line during three successiveiterations of step 806 of FIG. 8 . Between program pulses 900, 902 and904 verify pulses are applied to the selected word line during threesuccessive program-verify iterations of steps 806-808 of FIG. 8 todetermine whether threshold voltages of the memory cells are greaterthan the respective verify reference voltages.

Referring again to FIG. 8 , in process 800 a program failure is deemedto have occurred at step 816 if the program counter PC is greater thanor equal to program limit value PLV. Such a program failure typicallyindicates that the word line being programmed has experienced some typeof failure (e.g., an electrical short or some other failure). In suchinstances, the word line is determined to have failed.

In addition, in some instances the block that includes the failed wordline may be determined to have failed. In some instances the failedblock may be designated as a bad block, and no further memory operationsare performed on the bad block. As described above, in some memorydevices a program limit value PLV may be 28, or some other value.Waiting until this maximum number of program loops before determiningthat a word line failure and/or a block failure has occurred is wastefuland inefficient.

During a programming operation, a program loop count for a particularprogrammed state is a count of a number of program loops (e.g., steps806-820 of process 800 of FIG. 8 ) used to complete programming for theparticular programmed state. Without wanting to be bound by anyparticular theory, it is believed that programming failures, word linefailures, and/or block failures may be detected earlier based on programloop counts for one or more programmed states. Such techniques arereferred to herein as “early loop detection” techniques.

As used herein, PL_(X) is the program loop count for state X. Forexample, referring to FIG. 5B, if programmed state X=S1 memory cellscomplete programming in four program loops, PL_(S1)=4. Likewise, ifprogrammed state X=S4 memory cells complete programming in eight programloops, PL_(S4)=10, and so on.

For a population of memory cells, the program loop count for eachprogrammed state typically falls within a corresponding range of values.For example, for programmed state X memory cells program loop countPL_(X) may typically be between a corresponding lower limit (L_(X)) anda corresponding upper limit (U_(X)): L_(X)≤PL_(X)≤U_(X). For example,L_(X)=4 and U_(X)=7, or some other values.

During programming, if programmed state X memory cells have a programloop count PL_(X) that is not greater than or equal to correspondinglower limit L_(X) and less than or equal to corresponding upper limitU_(X), this may indicate that a program failure has occurred. As usedherein, this type of early loop detection test is referred to as an“absolute program loop count test.”

In addition, a difference in program loop counts for two differentprogrammed states also may be an indication of program failure. Forexample, a difference between a first program loop count PL_(Y) and asecond program loop count PL_(X) may typically be between acorresponding differential lower limit (L_(YX)) and a correspondingdifferential upper limit (U_(YX)): L_(YX)≤(PL_(Y)−PL_(X))≤U_(YX). Forexample, L_(YX)=9 and U_(YX)=12, or some other values.

During programming, if first programmed state Y memory cells have afirst program loop count PL_(Y) and second programmed state X memorycells have a second program loop count PL_(X), and if the difference inprogram loop counts (PL_(Y)−PL_(X)) is not greater than or equal tocorresponding differential lower limit L_(YX) and less than or equal tocorresponding differential upper limit U_(YX), this may indicate that aprogram failure has occurred. As used herein, this type of early loopdetection test is referred to as an “differential program loop counttest.”

Without wanting to be bound by any particular theory, it is believedthat early loop detection tests such as absolute program loop counttests and differential program loop count tests may be used duringprogramming operations to detect program failure earlier in theprogramming process than the maximum program count test described aboveprocess 800 of FIG. 8 (e.g., determining program failure if programcounter PC exceeds program limit value PLV).

That is, without wanting to be bound by any particular theory, it isbelieved that early loop detection tests such as absolute program loopcount tests and differential program loop count tests may provide afaster detection of programming failure, word line failure, and/or blockfailure than a maximum program count test.

Technology is described for programming processes that include earlyloop detection tests, such as an absolute program loop count test or adifferential program loop count test. In an embodiment, a programmingprocess includes an absolute program loop count test. In anotherembodiment, a programming process includes a differential program loopcount test.

In the embodiments described below, an early loop detection flag (ELD)is used to specify whether an optional early loop detection test shouldbe used to early detect programming failure, word line failure, and/orblock failure. For example, if ELD=0 the early loop detection testshould not be used, whereas if ELD=1, the early loop detection testshould be used to early detect programming failure, word line failure,and/or block failure.

FIG. 10A is a flowchart describing an embodiment of a process 1000 a forprogramming memory cells. In an example embodiment, process 1000 a isperformed on memory die 106 (FIG. 1 ) using the Control Circuitdiscussed above. For example, process 1000 a can be performed at thedirection of state machine 216 (FIG. 2 ). Process 1000 a also can beused to implement the full sequence programming discussed above.Additionally, process 1000 a can be used to implement each phase of amulti-phase programming process.

At step 1002, a word line is selected for programming. In an embodiment,the selected word line is coupled to one or more memory cells. In anembodiment, each memory cell coupled to the selected word line is in anerased state prior to programming. In an embodiment, during programmingeach memory cell coupled to the selected word line will be left in theerased state or programmed to one of multiple programmed states, such asthe programmed states depicted in FIGS. 5A-5C.

In step 1004, a programming voltage (V_(P)) is initialized to a startingprogram voltage V_(Pinit) (e.g., between about 12V to about 16V, or someother value) and a program counter PC maintained by state machine 216 isinitialized at 1. In a addition, an “early tested” flag ET isinitialized to 0. As described in more detail below, early tested flagET=0 indicates that an early loop detection test has not yet beenperformed, and early tested flag ET=1 indicates that an early loopdetection test has been performed and has passed.

In step 1006, a program pulse having a magnitude V_(P) is applied to theselected word line. In an embodiment, the group of memory cells beingconcurrently programmed are all connected to the selected word line. Ifa memory cell is to be programmed, then the corresponding bit linecoupled to the memory cell is grounded.

If a memory cell should remain at its current threshold voltage, thenthe corresponding bit line coupled to the memory cell is connected toVdd to inhibit programming. In an embodiment, the unselected word linesreceive one or more boosting voltages (e.g., between about 7V to about11V, or some other value) to perform boosting schemes known in the art.

In step 1006, the program pulse is applied to all memory cells connectedto the selected word line so that all of the connected memory cells areprogrammed concurrently. That is, they are programmed at the same timeor during overlapping times (both of which are considered concurrent).In this manner all memory cells connected to the selected word line willconcurrently have their threshold voltage change, unless they have beenlocked out from programming.

In step 1008, the memory cells are verified using the appropriate set ofverify reference voltages to perform one or more verify operations. Inan embodiment, the verification process is performed by testing whetherthe threshold voltages of the memory cells selected for programming havereached the appropriate verify reference voltage.

At step 1010, a determination is made whether early loop detection flagELD=1 and if early tested flag ET=0. As described above, at step 1004early tested flag ET is initialized to 0. As also described above, ifELD=1 the early loop detection technique should be used to detect blockfailure. Thus, on the first pass through step 1010, if the early loopdetection technique should be used to detect block failure, ELD=1 andET=0, and process 1000 a proceeds to step 1012 a.

At step 1012 a, a determination is made whether programming hascompleted for a particular programmed state X (e.g., X=S1 of FIG. 5B, orany other programmed state). If a determination is made at step 1012 athat programming for programmed state X has completed, then at step 1014a a determination is made whether program loop count PL_(X) is greaterthan or equal to corresponding lower limit L_(X) and less than or equalto corresponding upper limit U_(X). The test at step 1014 a is anexample of an absolute program loop count test.

If at step 1014 a a determination is made that program loop count PL_(X)is not greater than or equal to corresponding lower limit L_(X) and lessthan or equal to corresponding upper limit U_(X), then the absoluteprogram loop count test is considered to have failed and a status ofFAIL is reported in step 1016.

In an embodiment, upon receiving the FAIL status reported at step 1016,the Control Circuit determines that programming the memory cells coupledto the word line has failed. In an embodiment, upon receiving the FAILstatus reported at step 1016, the Control Circuit determines that theword line has failed. In another embodiment, upon receiving the FAILstatus reported at step 1016, the Control Circuit determines that theentire block of memory cells that includes the memory cells coupled tothe word line has failed.

In contrast, if at step 1014 a a determination is made that program loopcount PL_(X) is greater than or equal to corresponding lower limit L_(X)and less than or equal to corresponding upper limit U_(X), then theabsolute program loop count test is considered to have passed. At step1018 early tested flag is set to ET=1 to indicate that the early loopdetection test has been performed and has passed, and process 1000 aproceeds to step 1020.

In addition, if at step 1012 a a determination is made that programminghas not completed for a particular programmed state X, the absoluteprogram loop count test at step 1014 a should not be performed becausesuch testing is premature. Accordingly, process 1000 a proceeds to step1020. Likewise, if at step 1010 a determination is made that early loopdetection flag ELD≠1 (indicating that the early loop detection testshould not be used) or if early tested flag ET≠0 (indicating that theearly loop detection test has been performed and has passed), then theabsolute program loop count test at step 1014 a should not be performed.Accordingly, in both instances process 1000 a proceeds to step 1020.

In step 1020, the memory system counts the number of memory cells thathave not yet reached their respective target threshold voltagedistribution. That is, the system counts the number of memory cells thathave so far failed the verify process. This counting can be done bystate machine 216 (FIG. 2 ), controller 104 (FIG. 1 ), or other logic.

In an embodiment, each of sense blocks 212 (FIG. 2 ) stores the status(pass/fail) of their respective memory cells. In an embodiment, onetotal count reflects the total number of memory cells currently beingprogrammed that have failed the last verify step. In another embodiment,separate counts are kept for each data state.

In step 1022, a determination is made whether the count from step 1020is less than or equal to a predetermined limit. In an embodiment, thepredetermined limit is the number of bits that can be corrected by ECCduring a read process for the page of memory cells. If the number offailed cells is less than or equal to the predetermined limit, than theprogramming process can stop and a status of “PASS” is reported in step1024. In this situation, enough memory cells programmed correctly suchthat the few remaining memory cells that have not been completelyprogrammed can be corrected using ECC during the read process.

In some embodiments, the predetermined limit used in step 1022 is belowthe number of bits that can be corrected by ECC during a read process toallow for future/additional errors. When programming less than all ofthe memory cells for a page, or comparing a count for only one datastate (or less than all states), then the predetermined limit can be aportion (pro-rata or not pro-rata) of the number of bits that can becorrected by ECC during a read process for the page of memory cells. Insome embodiments, the limit is not predetermined. Instead, the limitchanges based on the number of errors already counted for the page, thenumber of program-erase cycles performed or other criteria.

If the number of failed memory cells is not less than the predeterminedlimit, then the programming process continues at step 1026 and theprogram counter PC is checked against program limit value. An exampleprogram limit value is PLV=28 although other values can be used. If theprogram counter PC is greater than or equal to program limit value PLV,then the program process is considered to have failed and a status ofFAIL is reported in step 1028.

If the program counter PC is not greater than or equal to program limitvalue PLV, then the process continues at step 1030 in which the ProgramCounter PC is incremented by 1 and program voltage V_(P) is stepped upto the next magnitude. For example, the next program pulse will have amagnitude greater than the previous pulse by a program step size ΔV_(P)(e.g., a step size of between about 0.1V to about 1.0V, or some othervalue).

Process 1000 a loops back to step 1006 and another program pulse isapplied to the selected word line so that another iteration (steps1006-1030) of programming process 1000 a is performed.

FIG. 10B is a flowchart describing an embodiment of a process 1000 b forprogramming memory cells. In an example embodiment, process 1000 b isperformed on memory die 106 (FIG. 1 ) using the Control Circuitdiscussed above. For example, process 1000 b can be performed at thedirection of state machine 216 (FIG. 2 ). Process 1000 b also can beused to implement the full sequence programming discussed above.Additionally, process 1000 b can be used to implement each phase of amulti-phase programming process.

At step 1002, a word line is selected for programming. In an embodiment,the selected word line is coupled to one or more memory cells. In anembodiment, each memory cell coupled to the selected word line is in anerased state prior to programming. In an embodiment, during programmingeach memory cell coupled to the selected word line will be left in theerased state or programmed to one of multiple programmed states, such asthe programmed states depicted in FIGS. 5A-5C.

In step 1004, a programming voltage (V_(P)) is initialized to a startingprogram voltage V_(Pinit) (e.g., between about 12V to about 16V, or someother value) and a program counter PC maintained by state machine 216 isinitialized at 1. In a addition, early tested flag ET is initialized to0. As described in more detail below, early tested flag ET=0 indicatesthat an early loop detection test has not yet been performed, and earlytested flag ET=1 indicates that an early loop detection test has beenperformed and has passed.

In step 1006, a program pulse having a magnitude V_(P) is applied to theselected word line. In an embodiment, the group of memory cells beingconcurrently programmed are all connected to the selected word line. Ifa memory cell is to be programmed, then the corresponding bit linecoupled to the memory cell is grounded.

If a memory cell should remain at its current threshold voltage, thenthe corresponding bit line coupled to the memory cell is connected toVdd to inhibit programming. In an embodiment, the unselected word linesreceive one or more boosting voltages (e.g., between about 7V to about11V, or some other value) to perform boosting schemes known in the art.

In step 1006, the program pulse is applied to all memory cells connectedto the selected word line so that all of the connected memory cells areprogrammed concurrently. That is, they are programmed at the same timeor during overlapping times (both of which are considered concurrent).In this manner all memory cells connected to the selected word line willconcurrently have their threshold voltage change, unless they have beenlocked out from programming.

In step 1008, the memory cells are verified using the appropriate set ofverify reference voltages to perform one or more verify operations. Inan embodiment, the verification process is performed by testing whetherthe threshold voltages of the memory cells selected for programming havereached the appropriate verify reference voltage.

At step 1010, a determination is made whether early loop detection flagELD=1 and if early tested flag ET=0. As described above, at step 1004early tested flag ET is initialized to 0. As also described above, ifELD=1 the early loop detection technique should be used to detect blockfailure. Thus, on the first pass through step 1010, if the early loopdetection technique should be used to detect block failure, ELD=1 andET=0, and process 1000 b proceeds to step 1012 b.

At step 1012 b, a determination is made whether programming hascompleted for a particular first programmed state Y (e.g., X=S7 of FIG.5B) and a particular second programmed state X (e.g., X=S1 of FIG. 5B).If a determination is made at step 1012 b that programming for firstprogrammed state Y and second programmed state X has completed, then atstep 1014 b a determination is made whether the difference in programloop counts (PL_(Y)−PL_(X)) is greater than or equal to correspondingdifferential lower limit L_(YX) and less than or equal to correspondingdifferential upper limit U_(YX). The test at step 1014 b is an exampleof an differential program loop count test.

If at step 1014 b a determination is made that the difference in programloop counts (PL_(Y)−PL_(X)) is not greater than or equal tocorresponding differential lower limit L_(YX) and less than or equal tocorresponding differential upper limit U_(YX), then the differentialprogram loop count test is considered to have failed and a status ofFAIL is reported in step 1016.

In an embodiment, upon receiving the FAIL status reported at step 1016,the Control Circuit determines that programming the memory cells coupledto the word line has failed. In an embodiment, upon receiving the FAILstatus reported at step 1016, the Control Circuit determines that theword line has failed. In another embodiment, upon receiving the FAILstatus reported at step 1016, the Control Circuit determines that theentire block of memory cells that includes the memory cells coupled tothe word line has failed.

In contrast, if at step 1014 b a determination is made that thedifference in program loop counts (PL_(Y)−PL_(X)) is greater than orequal to corresponding differential lower limit L_(YX) and less than orequal to corresponding differential upper limit U_(YX), then thedifferential program loop count test is considered to have passed. Atstep 1018 early tested flag is set to ET=1 to indicate that the earlyloop detection test has been performed and has passed, and process 1000b proceeds to step 1020.

In addition, if at step 1012 b a determination is made that programminghas not completed for the particular first programmed state Y and theparticular second programmed state X, the differential program loopcount test at step 1014 b should not be performed because such testingis premature. Accordingly, process 1000 b proceeds to step 1020.Likewise, if at step 1010 a determination is made that early loopdetection flag ELD 1 (indicating that the early loop detection testshould not be used) or if early tested flag ET 0 (indicating that theearly loop detection test has been performed and has passed), then thedifferential program loop count test at step 1014 b should not beperformed. Accordingly, in both instances process 1000 b proceeds tostep 1020.

In step 1020, the memory system counts the number of memory cells thathave not yet reached their respective target threshold voltagedistribution. That is, the system counts the number of memory cells thathave so far failed the verify process. This counting can be done bystate machine 216 (FIG. 2 ), controller 104 (FIG. 1 ), or other logic.

In an embodiment, each of sense blocks 212 (FIG. 2 ) stores the status(pass/fail) of their respective memory cells. In an embodiment, onetotal count reflects the total number of memory cells currently beingprogrammed that have failed the last verify step. In another embodiment,separate counts are kept for each data state.

In step 1022, a determination is made whether the count from step 1020is less than or equal to a predetermined limit. In an embodiment, thepredetermined limit is the number of bits that can be corrected by ECCduring a read process for the page of memory cells. If the number offailed cells is less than or equal to the predetermined limit, than theprogramming process can stop and a status of “PASS” is reported in step1024. In this situation, enough memory cells programmed correctly suchthat the few remaining memory cells that have not been completelyprogrammed can be corrected using ECC during the read process.

In some embodiments, the predetermined limit used in step 1022 is belowthe number of bits that can be corrected by ECC during a read process toallow for future/additional errors. When programming less than all ofthe memory cells for a page, or comparing a count for only one datastate (or less than all states), then the predetermined limit can be aportion (pro-rata or not pro-rata) of the number of bits that can becorrected by ECC during a read process for the page of memory cells. Insome embodiments, the limit is not predetermined. Instead, the limitchanges based on the number of errors already counted for the page, thenumber of program-erase cycles performed or other criteria.

If the number of failed memory cells is not less than the predeterminedlimit, then the programming process continues at step 1026 and theprogram counter PC is checked against program limit value. An exampleprogram limit value is PLV=28 although other values can be used. If theprogram counter PC is greater than or equal to program limit value PLV,then the program process is considered to have failed and a status ofFAIL is reported in step 1028.

If the program counter PC is not greater than or equal to program limitvalue PLV, then the process continues at step 1030 in which the ProgramCounter PC is incremented by 1 and program voltage V_(P) is stepped upto the next magnitude. For example, the next program pulse will have amagnitude greater than the previous pulse by a program step size ΔV_(P)(e.g., a step size of between about 0.1V to about 1.0V, or some othervalue).

Process 1000 b loops back to step 1006 and another program pulse isapplied to the selected word line so that another iteration (steps1006-1030) of programming process 1000 b is performed.

The example programming processes 1000 a and 1000 b of FIGS. 10A and10B, respectively, each perform a single early loop detection test. Inparticular, process 1000 a performs a single absolute program loop counttest in steps 1012 a-1018 of FIG. 10A, and process 1000 b performs asingle differential program loop count test in steps 1012 b-1018 of FIG.10B. In other embodiments, program processes may perform more than oneabsolute program loop count test and/or more than one differentialprogram loop count test to detect program failure, word line failureand/or block failure.

For example, in another exemplary embodiment, a programming process mayinclude an early loop detection test that includes a first absoluteprogram loop count test for first programmed state memory cells (e.g.,programmed state S1 in FIG. 5B), a second absolute program loop counttest for second programmed state memory cells (e.g., programmed state S4in FIG. 5B), and a third absolute program loop count test for thirdprogrammed state memory cells (e.g., programmed state S6 in FIG. 5B).

The programming process may determine that a program failure, word linefailure and/or block failure has occurred if any one of the three earlyloop detection tests fail, if a majority of the three early loopdetection tests fail, or if all three early loop detection tests fail.Alternatively, the results of the three early loop detection tests maybe weighted, such that one of the three early loop detection tests isgiven a higher weight in determining whether a program failure, wordline failure and/or block failure has occurred.

In another exemplary embodiment, a programming process may include anearly loop detection test that includes an absolute program loop counttest for first programmed state memory cells (e.g., programmed state S1in FIG. 5B), and a differential program loop count test for secondprogrammed state memory cells (e.g., programmed state S4 in FIG. 5B) andthird programmed state memory cells (e.g., programmed state S6 in FIG.5B).

The programming process may determine that a program failure, word linefailure and/or block failure has occurred if either the absolute programloop count test or the differential program loop count test has failed,or of both the absolute program loop count test and the differentialprogram loop count test have failed. Alternatively, the results of thetwo early loop detection tests may be weighted, such that one of theearly loop detection tests is given a higher weight in determiningwhether a program failure, word line failure and/or block failure hasoccurred.

One embodiment includes an apparatus that includes a block including aword line coupled to a plurality of memory cells, and a control circuitcoupled to the word line. The control circuit is configured to programthe plurality of memory cells by applying program pulses to the wordline in a plurality of program loops, determining a first count of anumber of the program loops used to complete programming a first subsetof the plurality of memory cells to a first programmed state, firstcomparing the first count to a corresponding first lower limit and acorresponding first upper limit, and determining whether programming theplurality of memory cells has failed based on a result of the firstcomparing step.

One embodiment includes an apparatus that includes a block including aword line coupled to a plurality of memory cells, and a control circuitcoupled to the word line. The control circuit is configured to programthe plurality of memory cells by applying program pulses to the wordline in a plurality of program loops, determining a first count of anumber of the program loops used to complete programming a first subsetof the plurality of memory cells to a first programmed state,determining a second count of a number of the program loops used tocomplete programming a second subset of the plurality of memory cells toa second programmed state, comparing a difference between the secondcount and the first count to a corresponding differential lower limitand a corresponding differential upper limit, and determining whetherprogramming the plurality of memory cells has failed based on a resultof the comparing step.

One embodiment includes a method that includes programming a pluralityof memory cells coupled to a word line by applying program pulses to theword line in a plurality of program loops, determining a first count ofa number of the program loops used to complete programming a firstsubset of the plurality of memory cells to a first programmed state,determining a second count of a number of the program loops used tocomplete programming a second subset of the plurality of memory cells toa second programmed state, comparing a difference between the secondcount and the first count to a corresponding differential lower and acorresponding differential upper limit, determining that a maximumnumber of program loops have not been performed, and determining from aresult of the comparing step that programming the plurality of memorycells has failed.

For purposes of this document, reference in the specification to “anembodiment,” “one embodiment,” “some embodiments,” or “anotherembodiment” may be used to describe different embodiments or the sameembodiment.

For purposes of this document, a connection may be a direct connectionor an indirect connection (e.g., via one or more other parts). In somecases, when an element is referred to as being connected or coupled toanother element, the element may be directly connected to the otherelement or indirectly connected to the other element via interveningelements. When an element is referred to as being directly connected toanother element, then there are no intervening elements between theelement and the other element. Two devices are “in communication” ifthey are directly or indirectly connected so that they can communicateelectronic signals between them.

For purposes of this document, the term “based on” may be read as “basedat least in part on.”

For purposes of this document, without additional context, use ofnumerical terms such as a “first” object, a “second” object, and a“third” object may not imply an ordering of objects, but may instead beused for identification purposes to identify different objects.

For purposes of this document, the term “set” of objects may refer to a“set” of one or more of the objects.

The foregoing detailed description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit to the precise form disclosed. Many modifications and variationsare possible in light of the above teaching. The described embodimentswere chosen in order to best explain the principles of the proposedtechnology and its practical application, to thereby enable othersskilled in the art to best utilize it in various embodiments and withvarious modifications as are suited to the particular use contemplated.It is intended that the scope be defined by the claims appended hereto.

1. An apparatus comprising: a block comprising a word line coupled to aplurality of memory cells; and a control circuit coupled to the wordline, the control circuit configured to program the plurality of memorycells by: applying program pulses to the word line in a plurality ofprogram loops; determining a first count of a number of the programloops used to complete programming a first subset of the plurality ofmemory cells to a first programmed state; first comparing the firstcount to a corresponding first lower limit and a corresponding firstupper limit; and determining whether programming the plurality of memorycells has failed based on a result of the first comparing step.
 2. Theapparatus of claim 1, wherein the control circuit is further configuredto: determine that the first count is less than the corresponding firstlower limit; and determine that programming the plurality of memorycells has failed.
 3. The apparatus of claim 1, wherein the controlcircuit is further configured to: determine that the first count isgreater than the corresponding first upper limit; and determine thatprogramming the plurality of memory cells has failed.
 4. The apparatusof claim 1, wherein the control circuit is further configured to:determine that the first count is greater than or equal to thecorresponding first lower limit and less than or equal to thecorresponding first upper limit; and determine that programming theplurality of memory cells has passed.
 5. The apparatus of claim 1,wherein the control circuit is further configured to: determine that thefirst count is less than the corresponding first lower limit; anddetermine from the result of the first comparing step that the block hasfailed.
 6. The apparatus of claim 1, wherein the control circuit isfurther configured to: determine that the first count is greater thanthe corresponding first upper limit; and determine from the result ofthe first comparing step that the block has failed.
 7. The apparatus ofclaim 1, wherein the control circuit is further configured to: determinethat the first count is greater than or equal to the corresponding firstlower limit and less than or equal to the corresponding first upperlimit; determine that a maximum number of program loops has beenperformed; and determine that programming the plurality of memory cellshas failed.
 8. The apparatus of claim 1, wherein the control circuit isfurther configured to program the plurality of memory cells by:determining a second count of a number of the program loops used tocomplete programming a second subset of the plurality of memory cells toa second programmed state; second comparing the second count to acorresponding second lower limit and a corresponding second upper limit;and determining whether programming the plurality of memory cells hasfailed based on a result of the second comparing step.
 9. The apparatusof claim 8, wherein the control circuit is further configured todetermine whether programming the plurality of memory cells has failedbased on the results of the first comparing step and the secondcomparing step.
 10. The apparatus of claim 8, wherein the controlcircuit is further configured to determine that programming theplurality of memory cells has failed if at least one of the following istrue: the first count is less than the corresponding first lower limit;the first count is greater than the corresponding first upper limit; thesecond count is less than the corresponding second lower limit; and thesecond count is greater than the corresponding second upper limit. 11.The apparatus of claim 8, wherein the control circuit is furtherconfigured to determine that programming the plurality of memory cellshas failed if all of the following are true: the first count is lessthan the corresponding first lower limit; the first count is greaterthan the corresponding first upper limit; the second count is less thanthe corresponding second lower limit; and the second count is greaterthan the corresponding second upper limit.
 12. An apparatus comprising:a block comprising a word line coupled to a plurality of memory cells;and a control circuit coupled to the word line, the control circuitconfigured to program the plurality of memory cells by: applying programpulses to the word line in a plurality of program loops; determining afirst count of a number of the program loops used to completeprogramming a first subset of the plurality of memory cells to a firstprogrammed state; determining a second count of a number of the programloops used to complete programming a second subset of the plurality ofmemory cells to a second programmed state; comparing a differencebetween the second count and the first count to a correspondingdifferential lower limit and a corresponding differential upper limit;and determining whether programming the plurality of memory cells hasfailed based on a result of the comparing step.
 13. The apparatus ofclaim 12, wherein the control circuit is further configured to programthe plurality of memory cells by: determining that the differencebetween the second count and the first count is less than thecorresponding differential lower limit; and determining that programmingthe plurality of memory cells has failed.
 14. The apparatus of claim 12,wherein the control circuit is further configured to program theplurality of memory cells by: determining that the difference betweenthe second count and the first count is greater than the correspondingdifferential upper limit; and determining that programming the pluralityof memory cells has failed.
 15. The apparatus of claim 12, wherein thecontrol circuit is further configured to program the plurality of memorycells by: determining that the difference between the second count andthe first count is greater than or equal to the correspondingdifferential lower limit and less than or equal to the correspondingdifferential upper limit; and determining that programming the pluralityof memory cells has passed.
 16. The apparatus of claim 12, wherein thecontrol circuit is further configured to program the plurality of memorycells by: determining that the difference between the second count andthe first count is less than the corresponding differential lower limit;and determining from the result of the comparing step that the block hasfailed.
 17. The apparatus of claim 12, wherein the control circuit isfurther configured to program the plurality of memory cells by:determining that the difference between the second count and the firstcount is greater than the corresponding differential upper limit; anddetermining from the result of the comparing step that the block hasfailed.
 18. The apparatus of claim 12, wherein the control circuit isfurther configured to determine that programming the plurality of memorycells has failed if any one of the following is true: the first count isless than a corresponding lower limit; the first count is greater than acorresponding upper limit; the difference between the second count andthe first count is less than the corresponding differential lower limit;and the difference between the second count and the first count isgreater than the corresponding differential upper limit.
 19. A methodcomprising: programming a plurality of memory cells coupled to a wordline by: applying program pulses to the word line in a plurality ofprogram loops; determining a first count of a number of the programloops used to complete programming a first subset of the plurality ofmemory cells to a first programmed state; determining a second count ofa number of the program loops used to complete programming a secondsubset of the plurality of memory cells to a second programmed state;comparing a difference between the second count and the first count to acorresponding differential lower and a corresponding differential upperlimit; determining that a maximum number of program loops have not beenperformed; and determining from a result of the comparing step thatprogramming the plurality of memory cells has failed.
 20. The method ofclaim 19, further comprising determining from the result of thecomparing step that the block has failed.